? semiconductor components industries, llc, 2002 april, 2002 rev. 7 1 publication order number: sn74ls74a/d sn74ls74a dual d-type positive edge-triggered flip-flop the sn74ls74a dual edge-triggered flip-flop utilizes schottky ttl circuitry to produce high speed d-type flip-flops. each flip-flop has individual clear and set inputs, and also complementary q and q outputs. information at input d is transferred to the q output on the positive-going edge of the clock pulse. clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. when the clock input is at either the high or the low level, the d input signal has no effect. mode select truth table operating mode inputs outputs operating mode s d c d d q q set reset (clear) *undetermined load a1o (set) load a0o (reset) l h l h h h l l h h x x x h l h l h h l l h h l h * both outputs will be high while both s d and c d are low, but the output states are unpredictable if s d and c d go high simultaneously. if the levels at the set and clear are near v il maximum then we cannot guarantee to meet the minimum level for v oh . h, h = high voltage level l, i = low voltage level x = don't care l, h (q) = lower case letters indicate the state of the referenced input i, h (q) = (or output) one set-up time prior to the high to low clock transition. guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 0.4 ma i ol output current low 8.0 ma low power schottky soic d suffix case 751a plastic n suffix case 646 14 1 14 1 soeiaj m suffix case 965 14 1 device package shipping ordering information sn74ls74an 14 pin dip 2000 units/box sn74ls74ad soic14 55 units/rail sn74ls74adr2 soic14 2500/tape & reel sn74ls74am soeiaj14 see note 1 sn74ls74amel soeiaj14 1. for ordering information on the eiaj version of the soic package, please contact your local on semiconductor representative. see note 1 http://onsemi.com
sn74ls74a http://onsemi.com 2 logic diagram (each flip-flop) logic symbol set (s d ) 4 (10) clear (cd ) 1 (13) clock 3 (11) d 2 (12) q 5 (9) q 6 (8) v cc = pin 14 gnd = pin 7 2 3 5 dq cp q c d 1 4 6 12 11 9 dq cp q c d 13 10 8 s d s d
sn74ls74a http://onsemi.com 3 dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.7 3.5 v v cc = min, i oh = max, v in = v ih or v il per truth table v out p ut low voltage 0.25 0.4 v i ol = 4.0 ma v cc = v cc min, v v or v v ol output low voltage 0.35 0.5 v i ol = 8.0 ma v in = v il or v ih per truth table i ih input high current data, clock set, clear 20 40 m a v cc = max, v in = 2.7 v i ih data, clock set, clear 0.1 0.2 ma v cc = max, v in = 7.0 v i il input low current data, clock set, clear 0.4 0.8 ma v cc = max, v in = 0.4 v i os output short circuit current (note 2) 20 100 ma v cc = max i cc power supply current 8.0 ma v cc = max 2. not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c, v cc = 5.0 v) limits symbol parameter min typ max unit test conditions f max maximum clock frequency 25 33 mhz figure 1 t plh clock clear set to output 13 25 ns figure 1 v cc = 5.0 v c l =15 p f t plh t phl clock, clear, set to output 25 40 ns figure 1 c l = 15 p f ac setup requirements (t a = 25 c) limits symbol parameter min typ max unit test conditions t w(h) clock 25 ns figure 1 t w(l) clear, set 25 ns figure 2 t data setup time e high 20 ns figure 1 v cc = 5.0 v t s data setu time high data setup time e low 20 ns figure 1 cc t h hold time 5.0 ns figure 1
sn74ls74a http://onsemi.com 4 figure 1. clock to output delays, data set-up and hold times, clock pulse width ac waveforms *the shaded areas indicate when the input is permitted to change for predictable output performance. d* cp q q 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t plh t phl t plh t phl t h(l) t s(l) t w(h) t w(l) t s(h) t h(h) 1 f max 1.3 v figure 2. set and clear to output delays, set and clear pulse widths t w 1.3 v 1.3 v t w 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v 1.3 v t plh t phl t plh t phl set clear q q
sn74ls74a http://onsemi.com 5 package dimensions 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n t 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87 n suffix plastic package case 64606 issue m
sn74ls74a http://onsemi.com 6 package dimensions d suffix plastic soic package case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
sn74ls74a http://onsemi.com 7 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z m suffix soeiaj package case 96501 issue o
sn74ls74a http://onsemi.com 8 on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sn74ls74a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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